In circuit design applications, repeaters, which can be inverting or non-inverting, along the interconnects within an integrated circuit (IC) network are inserted to reduce the interconnect delays to eliminate cycle (setup) time violations at the worst process corner. Traditionally, an initial timing at the worst process corner indicates the networks (nets) with setup time violations. Repeater insertion in those nets alleviates the setup time violations. A second timing at the best process corner is performed to identify the so-called fast paths with hold time violations. However, at the best process corner, timing in some paths in the IC network could be too fast giving rise to hold time violations. Special repeaters are then inserted to adequately increase the timing delays in the paths with hold time violations. One shortcoming of this two-step process is that the repeater insertion to reduce the timing delays in the first step is done without any consideration of the hold time violations and therefore can increase the number of nets with hold time violations. It should be appreciated that the first timing step at the worst process corner and the second timing step at the best process corner may be referred to as late timing mode and early timing mode, respectively.
For example, it is possible to have a sink, i.e., a destination, with a setup time violation at the worst process corner and a hold time violation at the best process corner. Thus, when attempting to reduce timing delays in the late mode without consideration of the early mode, a non-optimal solution that may adversely impact early mode timing as well as introduce extra repeaters may result. In such a scenario, the outcome of repeater insertion in the late-mode will be compromised with the repeater insertion in the early-mode.
Therefore, it is necessary to provide a repeater solution that alleviates setup time violations (late mode timing violations) and also alleviates hold time violations (early mode timing violations) at the same time.